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CY7C1347G
4-Mbit (128K x 36) Pipelined Sync SRAM
Features
* * * * * Fully registered inputs and outputs for pipelined operation 128K x 36 common IO architecture 3.3V core power supply (VDD) 2.5V/3.3V I/O power supply (VDDQ) Fast clock-to-output times
Functional Description[1]
The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 2.6 ns (250 MHz device). CY7C1347G supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC(R). The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Address Strobe from Processor (ADSP) or the Address Strobe from Controller (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the four Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state.
-- 2.6 ns (for 250-MHz device) * User-selectable burst counter supporting Intel(R) Pentium(R) interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous output enable * Offered in lead-free 100-Pin TQFP, lead-free and nonlead-free 119-Ball BGA package and 165-Ball FBGA package * "ZZ" sleep mode option and stop clock option * Available in industrial and commercial temperature ranges
Selection Guide
250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 325 40 200 MHz 2.8 265 40 166 MHz 3.5 240 40 133 MHz 4.0 225 40 Unit ns mA mA
Note 1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation Document #: 38-05516 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised May 22, 2007
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CY7C1347G
Logic Block Diagram
A0, A1, A
ADDRESS REGISTER
2
A[1:0]
MODE ADV CLK
Q1
ADSC ADSP
BW D DQD ,DQP D BYTE WRITE REGISTER DQC ,DQP C BYTE WRITE REGISTER DQB ,DQP B BYTE WRITE REGISTER DQA ,DQP A BYTE WRITE REGISTER
BURST COUNTER CLR AND LOGIC
Q0
DQD ,DQPD BYTE WRITE DRIVER DQC ,DQP C BYTE WRITE DRIVER DQB ,DQP B BYTE WRITE DRIVER DQA ,DQP A BYTE WRITE DRIVER
BW C
MEMORY ARRAY
SENSE AMPS
OUTPUT REGISTERS
OUTPUT BUFFERS E
BW B
DQs DQP A DQP B DQP C DQP D
BW A BWE
GW CE1 CE2 CE3 OE
ENABLE REGISTER
PIPELINED ENABLE
INPUT REGISTERS
ZZ
SLEEP CONTROL
Document #: 38-05516 Rev. *E
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CY7C1347G
Pin Configurations
100-Pin TQFP Pinout
A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
BYTE C
BYTE D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1347G
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA
BYTE B
BYTE A
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MODE A A A A A1 A0 NC/72M NC/36M VSS VDD NC/18M NC/9M A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1347G
Pin Configurations (continued) 119-Ball BGA Pinout
1 A B C D E F G H J K L M N P R T U VDDQ NC/288M NC/144M DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A CE2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC/72M NC 3 A A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A NC 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A NC 5 A A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A NC 6 A CE3 A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC/36M NC 7 VDDQ NC/576M NC/1G DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ
165-Ball FBGA Pinout
1 A B C D E F G H J K L M N P R
NC/288M NC/144M DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE
2
A A NC DQC DQC DQC DQC VSS DQD DQD DQD DQD NC NC/72M NC/36M
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC
NC
6
CE3 CLK
7
BWE GW
8
ADSC OE
9
ADV ADSP
10
A A NC/1G DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A
11
NC NC/576M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA NC/9M A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC/18M A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
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CY7C1347G
Pin Definitions
Name A0,A1,A IO Description InputAddress Inputs used to select one of the 128K address locations. Sampled at the rising Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feeds the 2-bit counter. InputByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the Synchronous SRAM. Sampled on the rising edge of CLK. InputGlobal Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, Synchronous a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). InputByte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must Synchronous be asserted LOW to conduct a byte write. Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation.
BWA,BWB, BWC,BWD GW
BWE CLK CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction Synchronous with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction Synchronous with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction Synchronous with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. Asynchronous When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputAdvance Input Signal, sampled on the rising edge of CLK. When asserted, it automatiSynchronous cally increments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. InputAddress Strobe from Controller, sampled on the rising edge of CLK. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ "Sleep" Input. This active HIGH input places the device in a non-time-critical "sleep" Asynchronous condition with data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down. IOBidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are placed in a tri-state condition. Power Supply Power supply inputs to the core of the device. Ground IO Power Supply IO Ground Ground for the core of the device. Power supply for the IO circuitry. Ground for the IO circuitry.
CE2
CE3
OE
ADV ADSP
ADSC
ZZ
DQA, DQB DQC, DQD DQPA, DQPB, DQPC, DQPD VDD VSS VDDQ VSSQ
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CY7C1347G
Pin Definitions (continued)
Name MODE IO InputStatic - Description Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up. No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M, NC/288M, NC/576M, and NC/1G are address expansion pins that are not internally connected to the die.
NC, NC/9M, NC/18M, NC/36M, NC/72M, NC/144M, NC/288M, NC/576M, NC/1G
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250 MHz device). The CY7C1347G supports secondary cache in systems using either a linear or interleaved burst sequence. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Address Strobe from Processor (ADSP) or the Address Strobe from Controller (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A[16:0]) is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the Output Register and onto the data bus within 2.6 ns (250 MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. After the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output tri-states immediately.
Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A[16:0] is loaded into the Address Register and the address advancement logic while being delivered to the RAM core. The write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle. ADSP-triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs and DQPs inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the write operation is controlled by BWE and BW[A:D] signals. The CY7C1347G provides byte write capability that is described in "Partial Truth Table for Read/Write" on page 9. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW[A:D]) input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1347G is a common IO device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs and DQPs inputs. Doing so tri-states the output drivers. As a safety precaution, DQs and DQPs are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a write to the desired byte(s). ADSC-triggered write accesses require a single clock cycle to complete. The address presented to A[16:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQs and DQPs is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1347G is a common IO device, the Output Enable (OE) must be deasserted HIGH before presenting data Page 6 of 21
Document #: 38-05516 Rev. *E
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CY7C1347G
to the DQs and DQPs inputs. Doing so tri-states the output drivers. As a safety precaution, DQs and DQPs are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1347G provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user-selectable through the MODE input. Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Sequence
First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 00 11 10 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 10 01 00
Linear Burst Sequence
First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 10 11 00 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 00 01 10
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ Active to snooze current ZZ Inactive to exit snooze current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min Max 40 2tCYC Unit mA ns ns ns ns
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CY7C1347G
Truth Table
The truth table for CY7C1347G follows.[2, 3, 4, 5, 6] Next Cycle Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Snooze Mode, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Add. Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 H L L L L X L L L L L X X H H X H X X H H X H CE2 X L X L X X H H H H H X X X X X X X X X X X X CE3 X X H X H X L L L L L X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP ADSC ADV WRITE X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L OE X X X X X X L H X L H H L L H X X L H L H X X CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State Q Tri-State D Q Tri-State Tri-State Q Q Tri-State D D Q Tri-State Q Tri-State D D
Notes: 2. X = "Do Not Care." H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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CY7C1347G
Partial Truth Table for Read/Write
The partial read/write truth table for CY7C1347G follows.[2, 7] Function Read Read Write Byte A - DQA Write Byte B - DQB Write Bytes B, A Write Byte C- DQC Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D- DQD Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X
Note 7. Table is only a partial listing of the byte write combinations. Any combination of BWx is valid. Appropriate write is based on which byte write is active.
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CY7C1347G
Maximum Ratings
Exceeding the maximum ratings may shorten the battery life of the device. User guidelines are not tested. Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage on VDD Relative to GND.........-0.5V to +4.6V Supply Voltage on VDDQ Relative to GND .......-0.5V to +VDD DC Voltage Applied to Outputs in High-Z State ........................................... -0.5V to VDD + 0.5V
DC Input Voltage ....................................... -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch Up Current ................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD VDDQ
3.3V 2.5V -5% -5%/+10% to VDD
Electrical Characteristics
Over the Operating Range [8, 9] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage IO Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[8] Input LOW Voltage[8] Input Leakage Current Except ZZ and MODE Input Current of MODE Input Current of ZZ IOZ IDD For 3.3V IO, IOH = -4.0 mA For 2.5V IO, IOH = -1.0 mA For 3.3V IO, IOL = 8.0 mA For 2.5V IO, IOL = 1.0 mA For 3.3V IO For 2.5V IO For 3.3V IO For 2.5V IO GND < VI < VDDQ Input = VSS Input = VDD Input = VSS Input = VDD Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 4-ns cycle, 250 MHz 5-ns cycle, 200 MHz 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz ISB1 Automatic CE Power Down Current--TTL Inputs Max. VDD, Device Deselected, VIN > VIH or VIN < VIL f = fMAX = 1/tCYC 4-ns cycle, 250 MHz 5-ns cycle, 200 MHz 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz ISB2 Automatic CE Power Down Current--CMOS Inputs All speeds Max. VDD, Device Deselected, VIN < 0.3V or VIN > VDDQ - 0.3V, f=0 -5 -5 30 5 325 265 240 225 120 110 100 90 40 2.0 1.7 -0.3 -0.3 -5 -30 5 Test Conditions Min 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max 3.6 VDD Unit V V V V V V V V V V A A A A A A mA mA mA mA mA mA mA mA mA
Notes 8. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC) > -2V (pulse width less than tCYC/2). 9. TPower-up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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CY7C1347G
Electrical Characteristics
Over the Operating Range (continued)[8, 9] Parameter ISB3 Description Automatic CE Power Down Current--CMOS Inputs Test Conditions Max. VDD, Device Deselected, or 4-ns cycle, 250 MHz VIN < 0.3V or VIN > VDDQ - 0.3V 5-ns cycle, 200 MHz f = fMAX = 1/tCYC 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz ISB4 Automatic CE Power Down Current--TTL Inputs Max. VDD, Device Deselected, VIN VIH or VIN VIL, f = 0 Min Max 105 95 85 75 45 Unit mA mA mA mA mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN CCLK CIO Description Input Capacitance Test Conditions 100 TQFP Max 5 5 5 119 BGA Max 5 5 7 165 FBGA Max 5 5 7 Unit pF pF pF
TA = 25C, f = 1 MHz, VDD = 3.3V. Clock Input Capacitance VDDQ = 3.3V Input/Output Capacitance
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 100 TQFP Package 30.32 6.85 119 BGA Package 34.1 14.0 165 FBGA Package 20.3 4.6 Unit C/W C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms 3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 R = 317 VDDQ 5 pF GND R = 351 10% ALL INPUT PULSES 90% 90% 10% 1 ns
1 ns
VT = 1.5V
(a) 2.5V I/O Test Load
OUTPUT Z0 = 50 2.5V
INCLUDING JIG AND SCOPE
(b)
R = 1667 VDDQ
(c)
ALL INPUT PULSES 10% 90% 90% 10% 1 ns
OUTPUT RL = 50 VT = 1.25V
5 pF
GND R = 1538
(a)
INCLUDING JIG AND SCOPE
1 ns
(b)
(c)
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CY7C1347G
Switching Characteristics
Over the Operating Range[14, 15] Parameter tPOWER Clock tCYC tCH tCL Output Times tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise ADV Hold After CLK Rise GW, BWE, BWX Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.3 0.3 0.3 0.3 0.3 0.3 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Setup Before CLK Rise ADSC, ADSP Setup Before CLK Rise ADV Setup Before CLK Rise GW, BWE, BWX Setup Before CLK Rise Data Input Setup Before CLK Rise Chip Enable Setup Before CLK Rise 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[11, 12, 13] Clock to High-Z[11, 12, 13] OE LOW to Output Valid OE LOW to Output OE HIGH to Output Low-Z[11, 12, 13] High-Z[11, 12, 13] 0 2.6 1.0 0 2.6 2.6 0 2.8 2.6 1.0 0 2.8 2.8 0 3.5 2.8 1.5 0 3.5 3.5 0 4.0 3.5 1.5 0 4.0 4.5 4.0 ns ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW 4.0 1.7 1.7 5.0 2.0 2.0 6.0 2.5 2.5 7.5 3.0 3.0 ns ns ns Description VDD(Typical) to the first Access[10] -250 Min 1 Max 1 -200 Min Max 1 -166 Min Max -133 Min 1 Max Unit ms
Notes 10. This part has an internal voltage regulator; tPOWER is the time that the power must be supplied above VDD(min) initially before a read or write operation can be initiated. 11. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of "AC Test Loads and Waveforms" on page 11. Transition is measured 200 mV from steady-state voltage. 12. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 13. This parameter is sampled and not 100% tested. 14. Timing references level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V on all data sheets. 15. Test conditions shown in (a) of "AC Test Loads and Waveforms" on page 11 unless otherwise noted.
Document #: 38-05516 Rev. *E
Page 12 of 21
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CY7C1347G
Switching Waveforms
Figure 2 shows read cycle timing waveforms.[16] Figure 2. Read Cycle Timing
t CYC
CLK
t CH
t
CL
t
ADS
t ADH
ADSP
t ADS tADH
ADSC
t AS tAH
ADDRESS
A1
t WES tWEH
A2
A3 Burst continued with new base address
GW, BWE, BW [A:D]
t CES tCEH
Deselect cycle
CE
t ADVS tADVH
ADV ADV suspends burst.
t OEV t OEHZ t CLZ t OELZ t CO t DOH t CHZ
OE
Data Out (Q)
High-Z
Q(A1)
t CO
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Single READ DON'T CARE UNDEFINED
BURST READ
Burst wraps around to its initial state
Note 16. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
Document #: 38-05516 Rev. *E
Page 13 of 21
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CY7C1347G
Switching Waveforms (continued)
Figure 3 shows write cycle timing waveforms.[16, 17] Figure 3. Write Cycle Timing
t CYC
CLK tCH t ADS ADSP ADSC extends burst t ADS tADH tADH tCL
t ADS ADSC t AS A1 tAH
tADH
ADDRESS
A2 Byte write signals are ignored for first cycle when ADSP initiates burst
A3
t WES tWEH
BWE, BW[A :B] t WES tWEH GW t CES CE t t ADVS ADVH ADV ADV suspends burst tCEH
OE t DS tDH
Data In (D)
High-Z
t OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE
DON'T CARE
UNDEFINED
Note 17. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWx LOW.
Document #: 38-05516 Rev. *E
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CY7C1347G
Switching Waveforms (continued)
Figure 4 shows read/write cycle timing waveforms.[16, 18, 19] Figure 4. Read/Write Cycle Timing
tCYC
CLK tCH t ADS ADSP tADH tCL
ADSC t AS tAH
ADDRESS
A1
A2
A3 t WES tWEH
A4
A5
A6
BWE, BW[A:D] t CES CE tCEH
ADV
OE tCO t DS tDH t OELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ Q(A2) Single WRITE D(A3) D(A5) D(A6)
Q(A4)
Q(A4+1) BURST READ
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
DON'T CARE
UNDEFINED
Notes 18. The data bus (Q) remains in High-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 19. GW is HIGH.
Document #: 38-05516 Rev. *E
Page 15 of 21
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CY7C1347G
Switching Waveforms (continued)
Figure 5 shows ZZ mode timing waveforms.[20, 21] Figure 5. ZZ Mode Timing
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
A LL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes 20. Device must be deselected when entering ZZ mode. See "Truth Table" on page 8 for all possible signal conditions to deselect the device. 21. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05516 Rev. *E
Page 16 of 21
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CY7C1347G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code CY7C1347G-133AXC CY7C1347G-133BGC CY7C1347G-133BGXC CY7C1347G-133BZC CY7C1347G-133BZXC CY7C1347G-133AXI CY7C1347G-133BGI CY7C1347G-133BGXI CY7C1347G-133BZI CY7C1347G-133BZXI 166 CY7C1347G-166AXC CY7C1347G-166BGC CY7C1347G-166BGXC CY7C1347G-166BZC CY7C1347G-166BZXC CY7C1347G-166AXI CY7C1347G-166BGI CY7C1347G-166BGXI CY7C1347G-166BZI CY7C1347G-166BZXI 200 CY7C1347G-200AXC CY7C1347G-200BGC CY7C1347G-200BGXC CY7C1347G-200BZC CY7C1347G-200BZXC CY7C1347G-200AXI CY7C1347G-200BGI CY7C1347G-200BGXI CY7C1347G-200BZI CY7C1347G-200BZXI 250 CY7C1347G-250AXC CY7C1347G-250BGC CY7C1347G-250BGXC CY7C1347G-250BZC CY7C1347G-250BZXC CY7C1347G-250AXI CY7C1347G-250BGI CY7C1347G-250BGXI CY7C1347G-250BZI CY7C1347G-250BZXI Package Diagram Package Type Operating Range Commercial
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free 51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free 51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free 51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free 51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free 51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free 51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free 51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free 51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Document #: 38-05516 Rev. *E
Page 17 of 21
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CY7C1347G
Package Diagrams
Figure 6. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.000.20 14.000.10
100 1 81 80
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0-7
R 0.08 MIN. 0.20 MAX.
0.600.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
Document #: 38-05516 Rev. *E
0.10
R 0.08 MIN. 0.20 MAX.
Page 18 of 21
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CY7C1347G
Package Diagrams (continued)
Figure 7.119-Ball BGA (14 x 22 x 2.4 mm), 51-85115
51-85115-*B
Document #: 38-05516 Rev. *E
Page 19 of 21
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CY7C1347G
Package Diagrams (continued)
Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180
BOTTOM VIEW PIN 1 CORNER TOP VIEW O0.05 M C PIN 1 CORNER O0.25 M C A B O0.50 -0.06 (165X)
+0.14 4 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 3 2 1 A B
1 A B
2
D E F G
1.00
C
C D E F G
15.000.10
15.000.10
14.00
H J K
H J K
7.00
L M N P R
L M N P R
A
A 5.00 10.00 B 13.000.10 B 0.15(4X) 13.000.10
1.00
1.40 MAX.
NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC
0.530.05
0.25 C
SEATING PLANE 0.36 C 0.350.06
0.15 C
51-85180-*A
Document #: 38-05516 Rev. *E
Page 20 of 21
(c) Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a registered trademark of International Business Machines, Inc. All product and company names mentioned in this document may be the trademarks of their respective holders. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
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CY7C1347G
Document History Page
Document Title: CY7C1347G 4-Mbit (128K x 36) Pipelined Sync SRAM Document Number: 38-05516 REV. ** *A *B ECN NO. 224364 276690 333625 Issue Date See ECN See ECN See ECN Orig. of Change Description of Change RKF VBL SYT New data sheet Changed TQFP package in Ordering Information section to lead-free TQFP Added comment of BG and BZ lead-free package availability Removed 225-MHz and 100-MHz speed grades Modified Address Expansion balls in the pinouts for 100 TQFP Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Replaced TBDs for JA and JC to their respective values on the Thermal Resistance table Changed the package name for 100 TQFP from A100RA to A101 Removed comment on the availability of BG lead-free package Updated the Ordering Information by shading and unshading MPNs as per availability Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page #1 from "3901 North First Street" to "198 Champion Court" Swapped typo CE2 and CE3 in the Truth Table column heading on Page #6 Modified test condition from VIH < VDD to VIH < VDD. Modified test condition from VDDQ < VDD to VDDQ < VDD Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the Electrical Characteristics Table. Replaced Package Name column with Package Diagram in the Ordering Information table. Replaced Package Diagram of 51-85050 from *A to *B Replaced Package Diagram of 51-85180 from ** to *A Updated the Ordering Information. Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Updated the Ordering Information table. Corrected write timing diagram on page 12
*C
419256
See ECN
RXU
*D *E
480124 1078184
See ECN See ECN
VKN VKN
Document #: 38-05516 Rev. *E
Page 21 of 21
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